A25QFO080QL datasheet(18/58 Pages) AMICC

18 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Read Data Bytes (READ)

The device is first selected by driving Chip Select ( S ) Low.

The instruction code for the Read Data Bytes (READ)

instruction is followed by a 3-byte address (A23-A0), each bit

being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on

Serial Data Output (DO), each bit being shifted out, at a

maximum frequency fR, during the falling edge of Serial Clock

(C).

The instruction sequence is shown in Figure 7. The first byte

addressed can be at any location. The address is

automatically incremented to the next higher address after

each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ)

instruction. When the highest address is reached, the

address counter rolls over to 000000h, allowing the read

sequence to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by

driving Chip Select ( S ) High. Chip Select ( S ) can be driven

High at any time during data output. Any Read Data Bytes

(READ) instruction, while an Erase, Program or Write cycle is

in progress, is rejected without having any effects on the

cycle that is in progress.

Figure 7. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

Instruction (03h)

High Impedance

MSB

810

01 2 3 4 5 6 7

Data Out 1

Data Out 2

24-Bit Address

28 29 30 31 32 33 34 35 36 37 38 39

23 22 21

3 21 0

6 54 32 10

Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.

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