TNETV1002IDZHK datasheet(55/102 Pages) TI1

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MCU Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

Some tools that only understand one type of processor may be configured for use with 5471 even when other

devices are on the ASIC scan chain. This is done by instructing the tools to place the other “unrecognized”

devices on the JTAG scan chain in their “BYPASS” modes. While the exact configuration methods are beyond

the scope of this document, the key is to understand the length of the instruction registers for the TAP

controllers so that the correct BYPASS instructions can be issued. For the 5471, this methodology would only

apply to the 5471 emulation mode where all three TAP controllers are in the JTAG scan chain (EMU1 =

EMU0 = ’1’ at TRST rising edge). The JTAG TAP controller instruction register lengths are listed in Table 4--8.

Table 4--8. JTAG TAP Controller Instruction Register Lengths

INSTRUCTION REGISTER LENGTH

JTAG TAP CONTROLLER

4bits

ARM7TDMIE core

8bits

C54x

™ DSP core

8bits

ASIC Logic TAP Controller

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