TMS28F008Axy,TMS28F800Axy

1048576 BY 8BIT/524288 BY 16BIT

AUTOSELECT BOOT BLOCK FLASH MEMORIES

SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998

39

POST OFFICE BOX 1443

timing requirements for TMS28F008AZy and TMS28F800AZy (commercial and extended

temperature ranges)

write/erase operations — CE-controlled writes

ALT.

SYMBOL

’28F008AZy 70

’28F800AZy 70

’28F008AZy80

’28F800AZy80

UNIT

SYMBOL

MIN

MAX

MIN

MAX

UNIT

tc( E )

Cycle time, write

tAVAV

70

80

ns

tc(E)OP

Cycle time, duration of programming operation

tEHQV1

6

6

µs

tc(E)ERB

Cycle time, erase operation (boot block)

tEHQV2

0.3

0.3

s

tc(E)ERP

Cycle time, erase operation (parameter block)

tEHQV3

0.3

0.3

s

tc(E)ERM

Cycle time, erase operation (main block)

tEHQV4

0.6

0.6

s

td(RPR)

Delay time, boot-block relock

tPHBR

100

100

ns

th(A)

Hold time, A0 − A18 (see Note 14)

tEHAX

0

0

ns

th(D)

Hold time, DQ valid

tEHDX

0

0

ns

th( W )

Hold time, WE

tEHWH

0

0

ns

th (VPP)

Hold time, VPP from valid status-register bit

tQVVL

0

0

ns

th(RP)

Hold time, RP at VHH from valid status-register bit

tQVPH

0

0

ns

th(WP)

Hold time, WP from valid status-register bit

tWHPL

0

0

ns

tsu(WP)

Setup time, WP before write operation

tELPH

50

50

ns

tsu(A)

Setup time, A0 − A18 (see Note 14)

tAVEH

50

50

ns

tsu(D)

Setup time, DQ

tDVEH

50

50

ns

tsu( W )

Setup time, WE before write operation

tWLEL

0

0

ns

tsu(RP)

Setup time, RP at VHH to CE going high

tPHHEH

100

100

ns

tsu( VPP)2

Setup time, VPP to CE going high

tVPEH

100

100

ns

tw(E)

Pulse duration, CE low

tELEH

50

50

ns

tw( EH)

Pulse duration, CE high

tEHEL

10

30

ns

trec(RPHE) Recovery time, RP high to CE going low

tPHEL

450

450

µs

NOTE 14: For 28F800 (8-bit configuration) A−1, A−1 −A18 with A−1 as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB

address.