LP8501 datasheet(29/51 Pages) TI1

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ack from slave

start

MSB Chip Addr LSB

SCL

ack from slave

MSB Register Addr LSB

MSB

Data

LSB

stop

ack from slave

nack from master

repeated start

data from slave

SDA

start

id =32h

w ack

address = 3Fh

ack

r ack

address 3Fh data

nack

stop

MSB Chip Address LSB

id = 32h

start

MSB Chip Addr LSB

ack

MSB Register Addr LSB

ack

MSB

Data LSB

ack

stop

ack from slave

SCL

SDA

start

id = 32h

ack

addr = 40h

ack

address 40h data

stop

ADR6

bit7

ADR5

bit6

ADR4

bit5

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR0

bit1

R/W

bit0

MSB

LSB

C Slave Address (chip address)

LP8501

www.ti.com

SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013

Figure 26. LP8501 Chip Address

Figure 27. Write cycle (w = write; SDA = “0”) id = chip address = 32h for LP8501

When a READ function is to be accomplished, a WRITE function must precede the READ function, as show above.

Figure 28. Read cycle (r = read; SDA = "1"), id = chip address = 32h for LP8501

Control Register Write Cycle

•

Master device generates start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master sends data byte to be written to the addressed register.

•

Slave sends acknowledge signal.

•

If master will send further data bytes, the slave’s control register address will be incremented by one after

acknowledge signal. In order to reduce program load time LP8501 supports address auto increment. Register

address is incremented after each 8 data bits. For example, the whole program memory page can be written

in one serial bus write sequence. Note: serial bus address auto increment is not supported for register

addresses from 16H to 1EH.

•

Write cycle ends when the master creates stop condition.

Control Register Read Cycle

•

Master device generates a start condition.

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