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LP3907SQ-PFX6W/NOPB bảng dữ liệu(PDF) 23 Page - Texas Instruments

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tên linh kiện LP3907SQ-PFX6W/NOPB
Giải thích chi tiết về linh kiện  Dual High-Current Step-Down DC-DC and Dual Linear Regulator
PDF  58 Pages
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Trang chủ  http://www.ti.com
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LP3907SQ-PFX6W/NOPB bảng dữ liệu(HTML) 23 Page - Texas Instruments

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EN1
nPOR
RDY1
EN2
RDY2
EN1
nPOR
RDY1
EN2
RDY2
0V
0V
Case1
Case2
EN1
nPOR
RDY1
EN2
RDY2
Case3
Counter
delay
t1
t2
t1
t2
Counter
delay
t1
t2
Counter
delay
23
LP3907
www.ti.com
SNVS511S – JUNE 2007 – REVISED APRIL 2016
Product Folder Links: LP3907
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Table 6. Power-Off Timing Specification
DESCRIPTION
MIN
NOM
MAX
UNIT
t1
Programmable delay from EN_T deassertion to VCC_Buck1 Off
1.5
ms
t2
Programmable delay from EN_T deassertion to VCC_Buck2 Off
2
ms
t3
Programmable delay from EN_T deassertion to VCC_LDO1 Off
3
ms
t4
Programmable delay from EN_T deassertion to VCC_LDO2 Off
6
ms
8.3.3 Flexible Power-On Reset (Power Good with Delay)
The LP3907 is equipped with an internal power-on-reset (POR) circuit which monitors the output voltage levels
on Bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs
are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. The time
delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms) 50 ms by default.
The system designer can choose the external pullup resistor (that is, 100 k
Ω) for the nPOR pin.
Figure 35. nPOR with Counter Delay



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