THS1041CPWR datasheet(25/42 Pages) TI1

tên linh kiện	THS1041CPWR

Giải thích chi tiết về linh kiện	10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

PDF	42 Pages

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nhà sản xuất	TI1 [Texas Instruments]

Trang chủ	http://www.ti.com

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THS1041

SLAS289C − OCTOBER 2001 − REVISED OCTOBER 2004

www.ti.com

PRINCIPLES OF OPERATION

clamp operation (continued)

Line Sync

Black

Level

Video at AIN

CLAMP

Figure 39. Example Waveforms for Line-Clamping to a Video Input Black Level

clamp DAC output voltage range and limits

When using the internal clamp DAC, the user must ensure that the desired dc clamp level at AIN+/− lies within

the voltage range VREFB to VREFT. This is because the clamp DAC voltage is constrained to lie within this range

VREFB to VREFT. Specifically:

VDAC

+ V

REFB ) (VREFT * VREFB)

(0.006

) 0.988

(DAC code) 1024)

DAC codes can range from 0 to 1023. Figure 40 graphically shows the clamp DAC output voltage versus the

DAC code.

VDAC

1023

VREFB + 0.006(VREFT−VREFB)

VREFB + 0.987(VREFT−VREFB)

DAC Code

VREFT

VREFB

Figure 40. Clamp DAC Output Voltage Versus DAC Register Code Value

If the desired dc level at AIN+/− does not lie within the voltage range VREFT to VREFB, then either the CLAMPIN

pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application

to move the AIN+/− input range into the CLAMP DAC voltage range.

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