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TFP401, TFP401A

SLDS120G – MARCH 2000 – REVISED MAY 2016

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9.4.2.3 Time-Staggered Pixel Output

This option works only in conjunction with the 2-pixel/clock mode (PIXS = high). Setting STAG = low time-

staggers the even- and odd-pixel outputs so as to reduce the amount of instantaneous current surge from the

power supply. Depending on the PCB layout and design, this can help reduce the amount of system ground

bounce and power-supply noise. The time stagger is such that in 2-pixel/clock mode, the even pixel is delayed

pixel/clock mode).

Depending on system constraints of output load, pixel rate, panel input architecture, and board cost, the

TFP401/401A drive-strength and staggered-pixel options allow flexibility to reduce system power-supply noise,

ground bounce, and EMI.

9.4.2.4 Power Management

The TFP401/401A offers several system power-management features.

The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode,

all output drivers except SCDT and CTL1 are driven to a high-impedance state while the rest of the device

circuitry remains active.

The TFP401/401A power down (PD = low) is a complete power down in that it powers down the digital core, the

analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except

for the PD input. The TFP401/401A does not respond to any digital or analog inputs until PD is pulled high.

Both PDO and PD have internal pullups, so if left unconnected they default the TFP401/401A to normal

operating modes.

9.4.2.5 Sync Detect

The TFP401/401A offers an output, SCDT, to indicate link activity. The TFP401/401A monitors activity on DE to

determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the

TFP401/401A considers the link inactive, and SCDT is driven low. While SCDT is low, if two DE transitions are

detected within 1600 pixel clock periods, the link is considered active, and SCDT is pulled high.

SCDT can be used to signal a system power management circuit to initiate a system power down when the link

is considered inactive. The SCDT can also be tied directly to the TFP401/401A PDO input to power down the

output drivers when the link is inactive. It is not recommended to use SCDT to drive the PD input, because once

in complete power-down, the analog inputs are ignored and the SCDT state does not change. An external

system power-management circuit to drive PD is preferred.