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TAS3108IADCPRG4 bảng dữ liệu(PDF) 12 Page - Texas Instruments

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tên linh kiện TAS3108IADCPRG4
Giải thích chi tiết về linh kiện  AUDIO DIGITAL SIGNAL PROCESSORS
PDF  63 Pages
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TAS3108IADCPRG4 bảng dữ liệu(HTML) 12 Page - Texas Instruments

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3.8.2
2 Channel Left Justified Timing
23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
19
18
20-BitMode
16-BitMode
15
14
MSB
LSB
32Clks
RightChannel
2-ChannelLeft-JustifiedStereoInput
T0034-02
4
5
9
8
1
4
5
1
0
0
0
23
22
1
19
18
15
14
MSB
LSB
4
5
9
8
1
4
5
1
0
0
0
SCLK
TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
In 2 channel left justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when
right channel data is transmitted. SCLK is a bit clock running at 64
× f
S which clocks in each bit of the
data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written
MSB first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused trailing
data-bit positions.
Figure 3-3. Left justified 64-fS Format
12
Physical Characteristics
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