công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

TAS3108IADCPRG4 bảng dữ liệu(PDF) 48 Page - Texas Instruments

Click here to check the latest version.
tên linh kiện TAS3108IADCPRG4
Giải thích chi tiết về linh kiện  AUDIO DIGITAL SIGNAL PROCESSORS
PDF  63 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI1 - Texas Instruments

TAS3108IADCPRG4 bảng dữ liệu(HTML) 48 Page - Texas Instruments

Back Button TAS3108IADCPRG4 Datasheet HTML 44Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 45Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 46Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 47Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 48Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 49Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 50Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 51Page - Texas Instruments TAS3108IADCPRG4 Datasheet HTML 52Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 48 / 63 page
background image
www.ti.com
8.5.3
Serial Audio Port Master Mode Signals (TAS3108/TAS3108IA)
tr(SCLKOUT)
tf(SCLKOUT)
tf(SCLKOUT)
tsk
tr(SCLKOUT)
tpd1(SCLKOUT2)
tpd1(SCLKOUT1)
tf(LRCLK), tr(LRCLK)
tpd2
tsu
th
SCLKOUT2
LRCLK
(Output)
SDOUT1
SDOUT2
SDOUT3
SDOUT4
SDIN1
SDIN2
SDIN3
SDIN4
SCLKOUT1
T0091-01
TAS3108, TAS3108IA
AUDIO DIGITAL SIGNAL PROCESSORS
SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(LRCLK)
Frequency LRCLK
CL = 30 pF
32(1)
192(1)
kHz
tr(LRCLK)
Rise time, LRCLK (2)
CL = 30 pF
12(1)
ns
tf(LRCLK)
Fall time, LRCLK (2)
Duty cycle is 50/50.
12(1)
ns
f(SCLKOUT)
Frequency, SCLKOUT1/SCLKOUT2
CL = 30 pF
64
25(1)
MHz
fS
(1)
tr(SCLKOUT)
Rise time, SCLKOUT1/SCLKOUT2
CL = 30 pF
20(1)
ns
tf(SCLKOUT)
Fall time, SCLKOUT1/SCLKOUT2
CL = 30 pF
20(1)
ns
tpd1(SCLKOUT1) Propagation delay, SCLKOUT1 falling edge to LRCLK edge
4(1)
ns
tpd1(SCLKOUT2) Propagation delay, SCLKOUT2 falling edge to LRCLK edge
4(1)
ns
tpd2
Propagation delay, SCLKOUT2 falling edge to SDOUT
4(1)
ns
tsu
Setup time, SDIN to SCLKOUT1 rising edge
20(1)
ns
th
Hold time, SDIN from SCLKOUT1 rising edge
23(1)
ns
t(SKEW)
Skew time, SCLKOUT1 to SCLKOUT2
3(1)
ns
(1)
This measurement in specified by design.
(2)
Rise time and fall time measured from 20% to 80% of maximum height of waveform.
Figure 8-3. TAS3108/TAS3108IA Serial Audio Port Master Mode Timing Waveforms
48
Electrical Specifications
Submit Documentation Feedback
Not Recommended for New Designs



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com