-

+

P

100 k:

100 k:

V

+

V

-

V

-

P

P

N

N

+IN

V

+

N

LMP7312

SNOSB32B – MARCH 2010 – REVISED MARCH 2013

www.ti.com

Figure 38. LMP7312 in High Impedance Mode

In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations.

MSB

LSB

Gain_1

Gain_0

EN_CL

Null_SW

Hi_Z

Gain Value (V/V)

Mode of Operation

0

0

0

0

0

0.096

Attenuation Mode

0

1

0

0

0

0.192

Attenuation Mode

1

0

0

0

0

0.384

Attenuation Mode

1

1

0

0

0

0.768

Attenuation Mode

1

0

1

0

0

1

Amplification Mode

1

1

1

0

0

2

Amplification Mode

x

x

x

x

1

–

High Impedance Output

x

x

x

1

0

1

Null Switch Mode

Daisy Chain

The LMP7312 supports daisy chaining of the serial data stream between multiple chips. To use this feature serial

data is clocked into the first chip SDI pin, and the next chip SDI pin is connected to the SDO pin of the first chip.

Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select

pin goes low on both chips and 5 bits have been clocked into the first chip the next 5 clock cycle begins moving

new configuration data into the second chip. With a full 10 clock cycles both chips have valid data and the chip

select pin of both chips should be brought high to prevent the data from overshooting.

20

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