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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LMF100CIWMX/NOPB bảng dữ liệu(PDF) 5 Page - Texas Instruments |
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LMF100CIWMX/NOPB bảng dữ liệu(HTML) 5 Page - Texas Instruments |
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5 / 42 page  Q Q D Not Recommended for New Designs LMF100 www.ti.com SNOSBG9B – JULY 1999 – REVISED JUNE 2015 6.4 Thermal Information LMF100 THERMAL METRIC(1) DW (SOIC) N (PDIP) UNIT 20 PINS 20 PINS RθJA Junction-to-ambient thermal resistance 63.8 49.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.2 41.1 °C/W RθJB Junction-to-board thermal resistance 31.8 30.4 °C/W ψJT Junction-to-top characterization parameter 5.7 18.3 °C/W ψJB Junction-to-board characterization parameter 31.3 30.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics for V + = +5 V and V− = −5 V The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V + = +5 V and V− = −5 V unless otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified. LMF100CCN LMF100CIWM PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX 9 9 13 Tested fCLK = 250 kHz, Is Maximum supply current Limit (1) mA TMIN to TMAX 13 No Input Signal Design TMIN to TMAX 13 Limit (2) 10000 f0 Center frequency 0.1 0.1 100000 Hz 0 35000 fCLK Clock frequency 5 5 3500000 Hz 00 ±0.2% ±0.2% ±0.8% Tested fCLK/f Clock to center frequency ratio VPin12 = 5 V or 0 Limit (1) TMIN to TMAX ±0.8% 0 deviation V, fCLK = 1 MHz Design TMIN to TMAX ±0.8% Limit (2) ±0.5% ±0.5% Q = 10, Mode 1, ±5% Tested VPin12 = 5 V or 0 Q Error (MAX) (3) Limit (1) TMIN to TMAX ±6% V, fCLK = 1 MHz Design TMIN to TMAX ±6% Limit (2) 0 0 ±0.4 Tested HOBP Bandpass gain at f0 fCLK = 1 MHz Limit (1) dB TMIN to TMAX ±0.4 Design TMIN to TMAX ±0.4 Limit (2) 0 0 ±0.2 Tested R1 = R2 = 10 k, HOLP DC Lowpass gain Limit (1) dB TMIN to TMAX ±0.2 fCLK = 250 kHz Design TMIN to TMAX ±0.2 Limit (2) ±5 ±5 ±15 Tested VOS1 DC Offset voltage (4) fCLK = 250 kHz Limit (1) mV TMIN to TMAX ±15 Design TMIN to TMAX ±15 Limit (2) (1) Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level). (2) Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested. (3) The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading Typical Characteristics. (4) Vos1, Vos2, and Vos3 refer to the internal offsets as discussed in Application Information. Copyright © 1999–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMF100 |
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