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LM97600CIUT/NOPB bảng dữ liệu(PDF) 35 Page - Texas Instruments |
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LM97600CIUT/NOPB bảng dữ liệu(HTML) 35 Page - Texas Instruments |
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35 / 58 page ![]() LM97600 www.ti.com SNAS600A – JULY 2012 – REVISED MARCH 2013 APPLICATION INFORMATION THE REFERENCE VOLTAGE The voltage reference for the LM97600 is derived from a 1.1 V bandgap reference, a buffered version of which is made available at pin 31, VBG, for user convenience. This output has an output current capability of ±100 μA. This reference voltage should be buffered if more current is required. The internal bandgap-derived reference voltage has a nominal value of 600 mV or 820 mV, as determined by the FSR pin and described in Configuration and Control There is no provision for the use of an external reference voltage, but the full-scale input voltage can be adjusted through a Configuration Register in the Extended Control mode, as explained in DEVICE CONTROL. Differential input signals up to the chosen full-scale level will be digitized to 7.6 bits. Signal excursions beyond the full-scale range will be clipped at the output. These large signal excursions will also activate the OR output for the time that the signal is out of range. See THE ANALOG INPUT. One extra feature of the VBG pin is that it can be used to raise the common mode voltage level of the LVDS outputs. The output offset voltage (VOS) is typically 800mV when the VBG pin is used as an output or left unconnected. To raise the LVDS offset voltage to a typical value of 1150mV the VBG pin can be connected directly to the supply rails. THE ANALOG INPUT The analog input is a differential one to which the signal source may be a.c. coupled or d.c. coupled. The full- scale input range is selected with the FSR pin to be 600 mVP-P or 820 mVP-P, or can be adjusted to values between 560 mVP-P and 840 mVP-P in the Extended Control mode through the Serial Interface. For best performance, it is recommended that the full-scale range be kept between 595 mVP-P and 805 mVP-P in the Extended Control mode because the internal DAC which sets the full-scale range is not as linear at the ends of its range. Table 9 gives the input to output relationship with the FSR pin high when the normal (non-extended) mode is used. With the FSR pin grounded, the millivolt values in Table 9 are reduced to 75% of the values indicated. In the Enhanced Control Mode, these values will be determined by the full scale range and offset settings in the Control Registers. Table 9. DIFFERENTIAL INPUT TO OUTPUT RELATIONSHIP (Non-Extended Control Mode, FSR High)(1) VIN+ VIN− Output Code VCM − 205mV VCM + 205mV 0000 0000 VCM − 102.5 mV VCM + 102.5 mV 0100 0000 0111 1111 / VCM VCM 1000 0000 VCM + 102.5 mV VCM −102.5 mV 1100 0000 VCM + 205mV VCM − 205mV 1111 1111 (1) The Full Scale Range registers for each of the four ADCs must be written consistent with the ADC Mode and Input Select settings The buffered analog inputs simplify the task of driving these inputs and the RC pole that is generally used at sampling ADC inputs is not required. If it is desired to use an amplifier circuit before the ADC, use care in choosing an amplifier with adequate noise and distortion performance and adequate gain at the frequencies used for the application. The Input impedance of VIN+ / VIN-in the d.c. coupled mode (VCMO pin not grounded) consists of a precision 100Ω resistor across the inputs and a capacitance from each of these inputs to ground. In the a.c. coupled mode, the input appears the same except there is also a resistor of 50K Ω between each analog input pin and the on-chip VCMO potential. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: LM97600 |
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