SN74LVC244ADBLE datasheet(5/34 Pages) TI1

5 / 34 page

SN74LVC244A

www.ti.com

SCAS414AA – NOVEMBER 1992 – REVISED JUNE 2016

Product Folder Links: SN74LVC244A

Submit Documentation Feedback

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±1000

(1)

All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.3 Recommended Operating Conditions

over recommended operating free-air temperature range (unless otherwise noted)

(1)

TA = 25°C

–40 TO +85°C

–40 TO +125°C

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

VCC Supply voltage

Operating

1.65

3.6

1.65

3.6

1.65

3.6

Data retention only

1.5

VIH

High-level

input voltage

VCC = 1.65 V to 1.95 V

0.65 × VCC

VCC = 2.3 V to 2.7 V

1.7

VCC = 2.7 V to 3.6 V

VIL

Low-level

input voltage

VCC = 1.65 V to 1.95 V

0.35 × VCC

VCC = 2.3 V to 2.7 V

0.7

VCC = 2.7 V to 3.6 V

0.8

Input voltage

5.5

Output voltage

VCC

IOH

High-level

output current

VCC = 1.65 V

–4

VCC = 2.3 V

–8

VCC = 2.7 V

–12

VCC = 3 V

–24

IOL

Low-level

output current

VCC = 1.65 V

VCC = 2.3 V

VCC = 2.7 V

VCC = 3 V

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2)

The package thermal impedance is calculated in accordance with JESD 51-7.

(3)

The package thermal impedance is calculated in accordance with JESD 51-5.

6.4 Thermal Information

THERMAL METRIC(1)

SN74LVC244A

UNIT

DB(2)

(SSOP)

DGV(2)

(TVSOP)

DW(2)

(SOIC)

ZQN(2)

(BGA)

N(2)

(PDIP)

NS(2)

(SO)

PW(2)

(TSSOP)

RGY(3)

(VQFN)

RWP(3)

(X1QFN)

20 PINS

RθJA

Junction-to-ambient

thermal resistance

108.1

128.7

90.9

198.7

61.6

90.1

114.7

50.3

79.9

°C/W

RθJC(top)

Junction-to-case (top)

thermal resistance

70.2

43.7

55.3

106.8

46.5

56.4

48.4

58.4

63.2

°C/W

RθJB

Junction-to-board

thermal resistance

63.3

70.2

58.8

143.1

42.5

57.7

65.6

28.3

46.4

°C/W

ψJT

Junction-to-top

characterization parameter

30.6

3.1

29.1

24.1

34.6

28.4

6.8

4.9

2.6

°C/W

ψJB

Junction-to-board

characterization parameter

62.9

69.5

58.3

119.6

42.4

57.2

65.1

28.4

46.3

°C/W

RθJC(bot)

Junction-to-case(bottom)

thermal resistance

—

n/a

—

22.7

27.3

°C/W

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