TUSB5052 datasheet(23/82 Pages) TI

23 / 82 page

4−3

Once the code is loaded, the MCU sets SDW = 1. This switches the memory map to normal-mode, i.e. the 16K-RAM

is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets

CONT = 1 (in the USBCTL register). This connects the device to the USB and results in normal USB device

enumeration.

4.1.3

GLOBCTL: Global Control Register

This register is used to control the MCU clock rate, power-down mode, and the CLKO frequency.

12/24

CLKOE

RSTP

RSV

R/W

R/O

BIT

NAME

RESET

FUNCTION

2−0

RSV

00b

Reserved = 0

RSTP

Reset-output polarity

RSTP = 0 RSTO output is active low

RSTP = 1 RSTO output is active high

CLKOE

0 = enable

1 = disable

6−5

C[1:0]

00b

Output clock frequency selection

00 = Output clock = 48 MHz

01 = Output clock = 24 MHz

10 = Output clock = 12 MHz

11 = Output clock = 6 MHz

12/24

This bit selects a 12-MHz or 24-MHz clock for the MCU

12/24=0 12 MHz

12/24=1 24 MHz

4.2

Buffers + I/O RAM Map

The address range from F800 to FFFF (2K bytes) is reserved for data buffers, setup packet, end-point descriptors

block (EDB) and all I/O. There are 128 locations reserved for memory mapped registers (MMR). Table 4−2 represents

the XDATA space allocation and access restriction for the DMA, UBM and MCU. Table 4−3 lists the memory-mapped

registers in the TUSB5052.

Table 4−2. XDATA Space

DESCRIPTION

ADDRESS RANGE

UBM ACCESS

DMA ACCESS

MCU ACCESS

Internal MMRs

(memory mapped registers)

FFFF

↑

FF80

(Only EDB-0)

(Only data register

and EDB-0)

Yes

EDB

FF7F

↑

Only for

Yes

EDB

(endpoint descriptors block)

↑

FF08

Only for

EDB update

Only for

EDB update

Yes

FF07

Setup packet

FF07

↑

Yes

Setup packet

↑

FF00

Yes

FEFF

Input endpoint_0 buffer

FEFF

↑

Yes

Input endpoint_0 buffer

↑

FEF8

Yes

FEF7

Output endpoint_0 buffer

FEF7

↑

Yes

Output endpoint_0 buffer

↑

FEF0

Yes

Data buffers

FEEF

↑

F800

Yes

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