TUSB5052 datasheet(47/82 Pages) TI

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6−5

6.1.4

DMACSR[4:3]: DMA Control and Status Register (2 UART Receive Channels)

This register is used to define the transaction time-out value. In addition, this register contains a completion code that

reports any errors or a time-out condition.

TEN

TXFT

RSV

R/W

R/C

R/O

BIT

NAME

RESET

FUNCTION

RSV

Reserved = 0

TXFT

Transfer time-out condition bit (see Table 6−3)

TXFT

TXFT = 0

DMA stopped transfer without time-out

TXFT = 1

DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear the EN bit in

DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the

MCU writes a 1. Writing a 0 has no effect.

6-2

C[4:0]

This field is used to define the transaction time-out value in 1 ms increments. This value is loaded to a down

counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the

counter decrements to zero, it sets TXFT =1 (in DMACSR register) and halts the DMA transfer. The counter starts

counting only when TEN = 1 and EN = 1 (in DMACDR) and the first byte has been received (see Figure 6−1).

00000 = Do not use if TEN is 1

00001 = 1-ms time-out

11111 = 31-ms time-out

TEN

Transaction time-out counter enable/disable bit

TEN = 0 Counter is disabled (does not time out).

TEN = 1 Counter is enabled.

Table 6−3. DMA IN-Termination Condition

IN-TERMINATION

TXFT

COMMENTS

UART error

UART error condition detected

UART time-out

This condition occurs when UART receiver has no more data for host (data starvation).

Counter

C[4:0]

TXFT

Load

SOF

TEN

Figure 6−1. Transaction Time-Out Diagram

6.2

Bulk Data I/O Using the EDB

The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters for IN

and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that (a) the MCU

initialized the EDBs, (b) DMA-continuous mode is being used, (c) double buffering is being used, and (d) the X/Y

toggle is controlled by the UBM.

IN Transaction (TUSB5052 to Host):

MCU initializes the IEDB (64-byte packet, and double-buffering is used) and the following DMA registers:

•

DMACSR: Defines the transaction time-out value.

•

DMACDR: Defines the IEDB being used and the DMA mode of operation (continuous-mode). Once this

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