TUSB5052 datasheet(54/82 Pages) TI

54 / 82 page

7−6

7.1.6

LSR[2:1]: Line-Status Registers (2 Registers)

These registers provide the status of the data transfer. DMA transfer is halted when any of OVR, PTE, FRE, BRK

or EXIT is 1.

RSV

TxE

RxF

BRK

FRE

PTE

OVR

R/O

R/C

BIT

NAME

RESET

FUNCTION

OVR

This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a status

interrupt (if enabled).

OVR = 0 No overrun error

OVR = 1 Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect.

PTE

This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and generates a status

interrupt (if enabled).

PTE = 0 No parity error in data received

PTE = 1 Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no effect.

FRE

This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and generates a status

interrupt (if enabled).

FRE = 0 No framing error in data received

FRE = 1 Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect.

BRK

This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and generates a status

interrupt (if enabled).

BRK = 0 No break condition

BRK = 1 A break condition in data received was detected. Clears when the MCU writes a 1. Writing a 0 has no

effect.

RxF

This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this bit since data

transfer is done by the DMA controller.

RxF = 0

No data in the RDR

RxF = 1

RDR contains data. Generates Rx interrupt (if enabled).

TxE

This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor this bit since

data transfer is done by the DMA controller.

TxE = 0

TDR is not empty

TxE = 1

TDR is empty. Generates Tx interrupt (if enabled).

6−7

RSV

Reserved = 0

CTS

MSR

MCR

(4) LCTS

(5) LDSR

(6) LRI

(7) LCD

(5) RTS

(4) DTR

(6) LRI

(7) LCD

(2) LOOP

DSR

DCD

RTS

DTR

Figure 7−1. MSR and MCR Registers in Loopback Mode

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