TMS320DM641 datasheet(160/171 Pages) TI

160 / 171 page

Ethernet Media Access Controller (EMAC)

160

June 2003 − Revised August 2004

SPRS222C

Table 4−69. Timing Requirements for EMAC MII Receive 10/100 Mbit/s† (see Figure 4−56)

NO.

−400

−500

−600

UNIT

MIN

MAX

tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high

th(MRCLKH-MRXD)

Hold time, receive selected signals valid after MRCLK high

† Receive selected signals include: MRXD3−MRXD0, MRXDV, and MRXER.

MRXD3−MRXD0 is driven by the PHY on the falling edge of MRCLK. MRXD3−MRXD0 timing must be met

during clock periods when MRXDV is asserted. MRXDV is asserted and deasserted by the PHY on the falling

edge of MRCLK. MRXER is driven by the PHY on the falling edge of MRCLK (xx = 00−01).

MRCLK (Input)

MRXD3−MRXD0,

MRXDV, MRXER (Inputs)

Figure 4−56. EMAC Receive Interface Timing

Table 4−70. Switching Characteristics Over Recommended Operating Conditions for EMAC

MII Transmit 10/100 Mbit/s‡ (see Figure 4−57)

NO.

−400

−500

−600

UNIT

MIN

MAX

td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid

‡ Transmit selected signals include: MTXD3−MTXD0, and MTXEN.

MTXD3−MTXD0 is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and

deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge.

MTCLK (Input)

MTXD3−MTXD0,

MTXEN (Outputs)

Figure 4−57. EMAC Transmit Interface Timing

TMS320DM641 bảng dữ liệu(PDF) 160 Page - Texas Instruments