TMS320DM641 datasheet(96/171 Pages) TI

96 / 171 page

Reset

June 2003 − Revised August 2004

SPRS222C

4.6

Reset

A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET

signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages

have reached their proper operating conditions. As a best practice, reset should be held low during power-up.

Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper

operating conditions and CLKIN should also be running at the correct frequency.

For information on peripheral selection at the rising edge of RESET, see the Device Configuration section of

this data manual.

4.6.1

Reset Electrical Data/Timing

Table 4−10. Timing Requirements for Reset (see Figure 4−9)

NO.

−400

−500

−600

UNIT

MIN

MAX

tw(RST)

Width of the RESET pulse

250

µs

tsu(boot)

Setup time, boot configuration bits valid before RESET high†

4E or 4C‡

th(boot)

Hold time, boot configuration bits valid after RESET high†

4P§

† AEA[22:19], LENDIAN, and HD5 are the boot configuration pins during device reset.

‡ E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.

Select the MIN parameter value, whichever value is larger.

§ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

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