TMS320DM641 datasheet(73/171 Pages) TI

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Device Configurations

June 2003 − Revised August 2004

SPRS222C

Read Accesses

Reserved

LOCKSTAT

R-0

R-1

Write Accesses

LOCK

W-0

Legend: R = Read only; R/W = Read/Write; -n = value after reset

Figure 2−4. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses

Table 2−4. PCFGLOCK Register Selection Bit Descriptions − Read Accesses

BIT

NAME

DESCRIPTION

31:1

Reserved

Reserved. Read-only, writes have no effect.

LOCKSTAT

Lock status bit.

Determines whether the PERCFG register is locked or unlocked.

= Unlocked, read accesses to the PERCFG register allowed.

= Locked, write accesses to the PERCFG register do not modify the register state [default].

Reads are unaffected by Lock Status.

Table 2−5. PCFGLOCK Register Selection Bit Descriptions − Write Accesses

BIT

NAME

DESCRIPTION

31:0

LOCK

Lock bits.

0x10C0010C = Unlocks PERCFG register accesses.

Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary

overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the

PERCFG register with the necessary enable bits set.

Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between

the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG

Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU

cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a

peripheral while it is disabled.

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