TMS320DM641 datasheet(153/171 Pages) TI

153 / 171 page

VCXO Interpolated Control (VIC)

153

June 2003 − Revised August 2004

SPRS222C

4.14

VCXO Interpolated Control (VIC)

The VIC can be used in conjunction with the Video Ports (VPs) to maintain synchronization of a video stream.

The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port.

4.14.1

VIC Device-Specific Information

The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9-bits

to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).

Typical D/A converters provide a discrete output level for every value of the digital word that is being converted.

This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by

choosing a few widely spaced output levels and interpolating values between them. The interpolating

mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output

represents the value of input code.

In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to

interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependent

on the resolution needed.

When the video port is used in transport stream interface (TSI) mode [currently not supported], the VIC port

is used to control the system clock, VCXO, for MPEG transport stream.

The VIC supports the following features:

•

Single interpolation for D/A conversion

•

Programmable precision from 9-to-16 bits

•

Interface for register accesses

For more detailed information on the DM641 and DM640 VCXO interpolated control (VIC) peripheral, see the

TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number

SPRU629).

4.14.2

VIC Peripheral Register Description(s)

Table 4−61. VCXO Interpolated Control (VIC) Port Registers

HEX ADDRESS RANGE

ACRONYM

01C4 C000

VICCTL

VIC control register

01C4 C004

VICIN

VIC input register

01C4 C008

VPDIV

VIC clock divider register

01C4 C00C − 01C4 FFFF

−

Reserved

TMS320DM641 bảng dữ liệu(PDF) 153 Page - Texas Instruments

TMS320DM641 bảng dữ liệu(HTML) 153 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL