TMS320DM641 datasheet(133/171 Pages) TI

133 / 171 page

Host-Port Interface (HPI) [DM641 Only]

133

June 2003 − Revised August 2004

SPRS222C

Table 4−40. Switching Characteristics Over Recommended Operating Conditions During Host-Port

Interface Cycles†‡ (see Figure 4−38 through Figure 4−41) [DM641 Only]

NO.

PARAMETER

−400

−500

−600

UNIT

MIN

MAX

td(HSTBL-HRDYH)

Delay time, HSTROBE low to HRDY high#

1.3

4P + 8

td(HSTBL-HDLZ)

Delay time, HSTROBE low to HD low impedance for an HPI read

td(HDV-HRDYL)

Delay time, HD valid to HRDY low

−3

toh(HSTBH-HDV)

Output hold time, HD valid after HSTROBE high

1.5

td(HSTBH-HDHZ)

Delay time, HSTROBE high to HD high impedance

td(HSTBL-HDV)

Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)

4P + 8

† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

# This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling edge of

HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal

address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full.

1st half-word

2nd half-word

HAS

HCNTL[1:0]

HR/W

HHWIL

HSTROBE†

HCS

HD[15:0] (output)

HRDY

† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 4−38. HPI16 Read Timing (HAS Not Used, Tied High) [DM641 Only]

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