TMS320DM641 datasheet(119/171 Pages) TI

119 / 171 page

External Memory Interface (EMIIF)

119

June 2003 − Revised August 2004

SPRS222C

4.8.3.4

HOLD/HOLDA Timing

Table 4−28. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module† (see Figure 4−30)

NO.

−400

−500

−600

UNIT

MIN

MAX

th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low

† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

Table 4−29. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA

Cycles for EMIFA Module†‡§ (see Figure 4−30)

NO.

PARAMETER

−400

−500

−600

UNIT

MIN

MAX

td(HOLDL-EMHZ)

Delay time, HOLD low to EMIFA Bus high impedance

td(EMHZ-HOLDAL)

Delay time, EMIF Bus high impedance to HOLDA low

td(HOLDH-EMLZ)

Delay time, HOLD high to EMIF Bus low impedance

td(EMLZ-HOLDAH)

Delay time, EMIFA Bus low impedance to HOLDA high

td(HOLDL-EKOHZ)

Delay time, HOLD low to AECLKOUTx high impedance

td(HOLDH-EKOLZ)

Delay time, HOLD high to AECLKOUTx low impedance

† E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.

‡ EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and

AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.

§ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,

ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−30.

¶ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay

time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

HOLD

HOLDA

EMIF Bus†

DSP Owns Bus

External Requestor

Owns Bus

DSP Owns Bus

DM641/DM640

AECLKOUTx‡

(EKxHZ = 0)

AECLKOUTx‡

(EKxHZ = 1)

† EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and

AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.

‡ The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,

ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−30.

Figure 4−30. HOLD/HOLDA Timing for EMIFA

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