DP8430V datasheet(52/56 Pages) NSC

52 / 56 page

130 AC Timing Parameters (Continued)

Unless otherwise stated VCC e 50V g10% 0 C k TA k 70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified

CL e 50 pF loads on all outputs except

CL e 150 pF loads on Q0–8 9 10 and WE or

CH e 50 pF loads on all outputs except

CH e 125 pF loads on RAS0–3 and CAS0–3 and

CH e 380 pF loads on Q0–8 9 10 and WE

Mode 1 Dual Access

DP8430V31V32V-33

Number

Symbol

Parameter Description

Min

Max

Min

Max

450

tSADDCKG

Row Address Setup to CLK High That

Asserts RAS following a GRANTB

Port Change to Ensure tASR e 0ns

451

tPCKRASG

CLK High to RAS Asserted

for Pending Access

452

tPCLKDL2

CLK to DTACK Asserted for Delayed

Accesses (Programmed as DTACK0)

453a

tPCKCASG0

CLK High to CAS Asserted

for Pending Access

(tRAH e 15 ns tASC e 0 ns)

453b

tPCKCASG1

CLK High to CAS Asserted

for Pending Access

(tRAH e 15 ns tASC e 10 ns)

453c

tPCKCASG2

CLK High to CAS Asserted

for Pending Access

(tRAH e 25 ns tASC e 0 ns)

453d

tPCKCASG3

CLK High to CAS Asserted

for Pending Access

101

108

(tRAH e 25 ns tASC e 10 ns)

454

tSBADDCKG

Bank Address Valid Setup to CLK High

that Asserts RAS for Pending Access

455

tSADSCK0

ADS Asserted Setup to CLK High

DP8430V bảng dữ liệu(PDF) 52 Page - National Semiconductor (TI)

DP8430V bảng dữ liệu(HTML) 52 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL