WM8993 datasheet(110/229 Pages) WOLFSON

110 / 229 page

WM8993

Production Data

PD, November 2010, Rev 4.0

110

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting DAC data to the WM8993 and outputting ADC data

from it. The digital audio interface uses four pins:

•

ADCDAT: ADC data output

•

DACDAT: DAC data input

•

LRCLK: Left/Right data alignment clock

•

BCLK: Bit clock, for synchronisation

The clock signals BCLK and LRCLK can be outputs when the WM8993 operates as a master, or

inputs when it is a slave (see Master and Slave Mode Operation, below).

Four different audio data formats are supported:

•

Left justified

•

Right justified

•

I2S

•

DSP mode

All four of these modes are MSB first. They are described in the following sections. Refer to the

“Signal Timing Requirements” section for timing information.

Time Division Multiplexing (TDM) is available in all four data format modes. The WM8993 can be

programmed to send and receive data in one of two time slots.

Two variants of DSP mode are supported - ‘Mode A’ and ‘Mode B’. PCM operation is supported

using the DSP mode.

MASTER AND SLAVE MODE OPERATION

The WM8993 digital audio interface can operate as a master or slave as shown in Figure 39 and

Figure 40.

Figure 39 Master Mode

Figure 40 Slave Mode

The Audio Interface output control is illustrated above. The master mode control register AIF_MSTR1

determines whether the WM8993 generates the clock signals. The AIF_MSTR1 register field is

defined in Table 72.

BCLK and LRCLK can be enabled as outputs in Slave mode, allowing mixed Master/Slave operation

- see “Digital Audio Interface Control”.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Audio

Interface (3)

AIF_MSTR1

Audio Interface 1 Master Mode Select

0 = Slave mode

1 = Master mode

Table 72 Audio Interface Master/Slave Control

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