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WM8993 bảng dữ liệu(PDF) 88 Page - Wolfson Microelectronics plc |
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WM8993 bảng dữ liệu(HTML) 88 Page - Wolfson Microelectronics plc |
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88 / 229 page ![]() WM8993 Production Data w PD, November 2010, Rev 4.0 88 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1 DCS_ENA_CHAN_1 0 DC Servo enable for HPOUT1R 0 = disabled 1 = enabled 0 DCS_ENA_CHAN_0 0 DC Servo enable for HPOUT1L 0 = disabled 1 = enabled R87 (57h) DC Servo 3 15:8 DCS_DAC_WR_VA L1 [7:0] 0000 0000 DC Offset value for HPOUT1Rin DAC Write DC Servo mode. Two’s complement format. LSB is 0.25mV. Range is -32mV to +31.75mV 7:0 DCS_DAC_WR_VA L0 [7:0] 0000 0000 DC Offset value for HPOUT1Lin DAC Write DC Servo mode. Two’s complement format. LSB is 0.25mV. Range is -32mV to +31.75mV R88 (58h) DC Servo Readback 0 9:8 DCS_CAL_COMPL ETE [1:0] 00 DC Servo Complete status 0 = DAC Write or Start-Up DC Servo mode not completed. 1 = DAC Write or Start-Up DC Servo mode complete. Bit [1] = HPOUT1R Bit [0] = HPOUT1L 5:4 DCS_DAC_WR_CO MPLETE [1:0] 00 DC Servo DAC Write status 0 = DAC Write DC Servo mode not completed. 1 = DAC Write DC Servo mode complete. Bit [1] = HPOUT1R Bit [0] = HPOUT1L 1:0 DCS_STARTUP_C OMPLETE [1:0] 00 DC Servo Start-Up status 0 = Start-Up DC Servo mode not completed. 1 = Start-Up DC Servo mode complete. Bit [1] = HPOUT1R Bit [0] = HPOUT1L Table 56 DC Servo Enable and Start-Up Modes DC SERVO ACTIVE MODES The DC Servo modes described above are suitable for initialising the DC offset correction circuit on the Headphone outputs as part of a controlled start-up sequence which is executed before the signal path is fully enabled. Additional modes are available for use whilst the signal path is active; these modes may be of benefit following a large change in signal gain, which can lead to a change in DC offset level. Periodic updates may also be desirable to remove slow drifts in DC offset caused by changes in parameters such as device temperature. The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and DCS_ENA_CHAN_1 respectively, as described earlier in Table 56. Writing a logic 1 to DCS_TRIG_SINGLE_n initiates a single DC offset measurement and adjustment to the associated output; (‘n’ = 0 for Left channel, 1 for Right channel). This will adjust the DC offset correction on the selected channel by no more than 1LSB (0.25mV). Setting DCS_TIMER_PERIOD_01 to a non-zero value will cause a single DC offset measurement and adjustment to be scheduled on a periodic basis. Periodic rates ranging from every 0.52s to in excess of 2hours can be selected. |
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