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WM5102 bảng dữ liệu(PDF) 98 Page - Wolfson Microelectronics plc |
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WM5102 bảng dữ liệu(HTML) 98 Page - Wolfson Microelectronics plc |
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98 / 334 page ![]() WM5102 Production Data w PD, June 2014, Rev 4.2 98 Figure 39 Digital Core Sample Rate Control (External Digital Interfaces) The input signal paths may be selected as input to the digital mixers or signal processing functions. The sample rate for the input signal paths is configured using the IN_RATE register. The output signal paths are derived from the respective output mixers. The sample rate for the output signal paths is configured using the OUT_RATE register. The sample rate of the AEC Loopback path is also set by the OUT_RATE register. The AIFn RX inputs may be selected as input to the digital mixers or signal processing functions. The AIFn TX outputs are derived from the respective output mixers. The sample rates for digital audio interfaces (AIF1, AIF2 and AIF3) are configured using the AIF1_RATE, AIF2_RATE and AIF3_RATE registers respectively. The SLIMbus interface supports up to 8 input channels and 8 output channels. The sample rate of each channel can be configured independently, using the SLIMTXn_RATE and SLIMRXn_RATE registers. Note that the SLIMbus interface provides simultaneous support for SYSCLK-referenced and ASYNCCLK-referenced sample rates on different channels. For example, 48kHz and 44.1kHz SLIMbus audio paths can be simultaneously supported. |
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