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DP8390D bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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DP8390D bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI) |
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4 / 56 page ![]() Connection Diagrams Plastic Chip Carrier TLF8582 – 5 Dual-In-Line Package TLF8582 – 4 Order Number DP8390DN or DP8390DV See NS Package Number N48A or V68A 50 Pin Descriptions BUS INTERFACE PINS Symbol DIP Pin No Function Description AD0 – AD15 1 – 12 IOZ MULTIPLEXED ADDRESSDATA BUS 14–17 Register Access with DMA inactive CS low and ACK returned from NIC pins AD0 – AD7 are used to readwrite register data AD8 – AD15 float during IO transfers SRD SWR pins are used to select direction of transfer Bus Master with BACK input asserted During t1 of memory cycle AD0 – AD15 contain address During t2 t3 t4 AD0 – AD15 contain data (word transfer mode) During t2 t3 t4 AD0 – AD7 contain data AD8 – AD15 contain address (byte transfer mode) Direction of transfer is indicated by NIC on MWR MRD lines ADS0 18 IOZ ADDRESS STROBE 0 Input with DMA inactive and CS low latches RA0–RA3 inputs on falling edge If high data present on RA0–RA3 will flow through latch Output when Bus Master latches address bits (A0–A15) to external memory during DMA transfers 4 |
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