DAC7750IPWPR datasheet(29/53 Pages) TI1

29 / 53 page

Bit

Boundary

Phase

Continuous

2200 Hz

(space)

1200 Hz

(mark)

Time

5.5 mA

6.5 mA

6.0 mA

Bit Cell Time = 833 s

DAC7750, DAC8750

www.ti.com

SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

Product Folder Links: DAC7750 DAC8750

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NOTE: DC current = 6 mA.

Figure 58. Output Current vs Time

Table 6. HART-IN Terminal Characteristics

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input impedance

HART signal ac-coupled into terminal

kΩ

Output current (peak-to-peak)

Input signal of 500 mV (peak-to-peak)

0.9

1.1

8.4.6.2 Implementing HART in All Current Output Modes

The use of the HART-IN terminal to implement HART modulation is limited to the case where the RANGE bits of

the Control Register are set to the 4-mA to 20-mA range. If it is desirable to implement HART in all current-output

modes, refer to Implementing HART In All Current Output Modes in Application Information.

8.5 Programming

Table 11 shows the available commands and registers on the DACx750 devices. No operation, read operation,

and watchdog timer refer to commands and are not explicit registers. For more information on these commands,

see the Read Operation and Watchdog Timer sections.

8.5.1 Serial Peripheral Interface (SPI)

The device is controlled over a versatile four-wire serial interface (SDI, SDO, SCLK, and LATCH) that operates at

clock rates of up to 30 MHz and is compatible with SPI, QSPI™, Microwire, and digital signal processing (DSP)

standards. The SPI communication command consists of a write address byte and a data word for a total of 24

bits. The timing for the digital interface is shown in Figure 1, Figure 2, and Figure 3.

8.5.1.1 SPI Shift Register

The default frame is 24 bits wide (see Frame Error Checking for 32-bit frame mode) and begins with the rising

edge of SCLK that clocks in the MSB. The subsequent bits are latched on successive rising edges of SCLK. The

default 24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in Table 7.

Table 7. Default SPI Frame

BIT 23:BIT 16

BIT 15:BIT 0

Address byte

Data word

The host processor must issue 24 bits before it issues a rising edge on the LATCH terminal. Input data bits are

clocked in regardless of the LATCH terminal and are unconditionally latched on the rising edge of LATCH. By

default, the SPI shift register resets to 0x000000 at power on or after a reset.

8.5.1.2 Write Operation

A write operation is accomplished when the address byte is set according to Table 8. For more information on

the DACx750 registers, see the Register Maps section.

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