DP83266 datasheet(73/152 Pages) NSC

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70 Control Information (Continued)

Interrupt Condition Register (ICR)

The Interrupt Condition Register (ICR) collects unmasked interrupts from the Event Registers Interrupts are categorized into

Ring Events Token and Timer Events Counter Events and Error and Exceptional Status Events If the bit in the Interrupt Mask

Register (IMR) and the corresponding bit in the ICR are set to One the INT0 pin is forced low and thus triggers an interrupt

Note

Bits are cleared ONLY by clearing underlying conditions (Mask bit andor Event Bit) in the appropriate Event Register

Access Rules

Address

Read

Write

02Eh

Always

Data Ignored

ESE

IERR

RES

COE

CIE

TTE

RNG

Bit

Symbol

Description

ESE

Exception Status Event Interrupt

Is set if any unmasked bits in the Exception Status Register are set

IERR

Internal Error Interrupt

Is set if any bits in the Internal Event Register are set

D5 – D4

RES

Reserved

COE

Counter Overflow Event Interrupt

Is set if any unmasked bits in the Counter Overflow Latch Register

are set

CIE

Counter Increment Event Interrupt

Is set if any unmasked bits in the Counter Increment Latch Register

are set

TTE

Token and Timer Event Interrupt

Is set if any unmasked bits in the Token and Timer Event Latch

RNG

Ring Event Interrupt

Is set if any unmasked bits in the Ring Event Latch Registers are set

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