TMS320VC5416 datasheet(74/98 Pages) TI

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5.5.7

Reset, BIO, Interrupt, and MP/MC Timings

BIO

CLKOUT

RS, INTn, NMI

X2/CLKIN

th(BIO)

th(RS)

tsu(INT)

tw(BIO)S

tsu(BIO)

tw(RSL)

tsu(RS)

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Table 5-17 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-15,

Figure 5-16, and Figure 5-17).

Table 5-17. Reset, BIO, Interrupt, and MP/MC Timing Requirements

5416-120

5416-160

UNIT

MIN

MAX

th(RS)

Hold time, RS after CLKOUT low(1)

th(BIO)

Hold time, BIO after CLKOUT low(1)

th(INT)

Hold time, INTn, NMI, after CLKOUT low(1)(2)

th(MPMC)

Hold time, MP/MC after CLKOUT low(1)

tw(RSL)

Pulse duration, RS low(3)(4)

4H + 3

tw(BIO)S

Pulse duration, BIO low, synchronous

2H + 3

tw(BIO)A

Pulse duration, BIO low, asynchronous

tw(INTH)S

Pulse duration, INTn, NMI high (synchronous)

2H + 2

tw(INTH)A

Pulse duration, INTn, NMI high (asynchronous)

tw(INTL)S

Pulse duration, INTn, NMI low (synchronous)

2H + 2

tw(INTL)A

Pulse duration, INTn, NMI low (asynchronous)

tw(INTL)WKP

Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup

tsu(RS)

Setup time, RS before X2/CLKIN low(2)(1)

tsu(BIO)

Setup time, BIO before CLKOUT low(1)

tsu(INT)

Setup time, INTn, NMI, RS before CLKOUT low(1)

tsu(MPMC)

Setup time, MP/MC before CLKOUT low(1)

(1)

These inputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT,

however, if setup and hod timings are met, the input will be recognized on the CLKOUT edge referenced.

(2)

The external interrupts (INT0-INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples thse

inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a1-0-0 sequence at the timing

that is corresponding to three CLKOUTs sampling sequence.

(3)

If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure

synchronization and lock-in of the PLL.

(4)

Note that RS may cause a change in clock frequency, therefore changing the value of H.

Figure 5-15. Reset and BIO Timings

Electrical Specifications

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