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WRITE

CLKOUT

A[22:0]

D[15:0]

R/W

PS/DS/IS

Leading

Cycle

Write

Cycle

MSTRB or IOSTRB

Trailing

Cycle

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

Figure 3-15. Memory Write and I/O Write Bus Sequence

The enhanced interface also provides the ability for DMA transfers to extend to external memory. For

more information on DMA capability, see the DMA sections that follow.

The enhanced interface improves the low-power performance already present on the TMS320C5000™

DSP platform by switching off the internal clocks to the interface when it is not being used. This

power-saving feature is automatic, requires no software setup, and causes no latency in the operation of

the interface.

Additional features integrated in the enhanced interface are the ability to automatically insert

bank-switching cycles when crossing 32K memory boundaries (see Section 3.6.2), the ability to program

up to 14 wait states through software (see Section 3.6.1), and the ability to divide down CLKOUT by a

factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative to wait states when interfacing to

slower external memory or peripheral devices. While inserting wait states extends the bus sequence

during read or write accesses, it does not slow down the bus signal sequences at the beginning and the

end of the access. Dividing down CLKOUT provides a method of slowing the entire bus sequence when

necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the bank-switching

control register (BSCR) (see Table 3-5).

Functional Overview

TMS320VC5416 bảng dữ liệu(PDF) 36 Page - Texas Instruments