MAC7101CVF datasheet(28/48 Pages) MOTOROLA

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MAC7100 Microcontroller Family Hardware Specifications

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Electrical Characteristics

3.10.4 ATD Timing Specifications

6 Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for

each 8 to 12

°C, in the ambient temperature range of 50 to 125 °C.

7 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs

greater than VRH and 0x000 for values less than VRL. This assumes that VDDA ≥ AVRH and VRL ≥ VSSA due to the

presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.

8 Coupling Ratio, K, is defined as the ratio of the output current, IOUT, measured on the pin under test to the injection

current, IINJ, when both adjacent pins are overstressed with the specified injection current. K = IOUT ÷ IINJ. The input

voltage error on the channel under test is calculated as Verr = IINJ x K x RS.

9 Total injection current is determined by the number of channels injecting (for example, 15), external injection voltage

(VINJ –VPOSCLAMP, or VINJ – VNEGCLAMP), and the external source impedance, Rs, wherein all input channels have

the same values. To determine the error voltage on the converted channel, only the two adjacent channels are

expected to contribute to the error voltage: Verrj = (VINJ – VCLAMP) × K × 2.

10 For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, Cf ≥ 1024 × CSAMP. The

value of CSAMP in the new design may be reduced, or increased slightly.

Table 30. ATD Performance Specifications 1

1 All voltages referred to VSSA, VDDA = 5.0 V±10%, ATD clock = 2.1 Mhz., –40 to 125 °C.

Num C

Rating

Symbol

Min

Typ

Max

Unit

D 10-bit Resolution

LSB

—

D 10-bit Differential Nonlinearity 2

2 Note: 1 LSB = 1 Count (At VREF = 5.12 V, one 8 bit count = 20 mV, one 10-bit count = 5 mV)

DNL

–1

—

Counts

D 10-bit Integral Nonlinearity 2

INL

–2

—

Counts

D 10-bit Absolute Error 2, 3

3 These values include quantization error which is inherently 1/2 count for any A/D converter.

–2.5

—

2.5

Counts

D Max input Source Impedance 4

4 This value is based on error attributed to the specified leakage value of TBD nA resulting in an error of less than 1/2

LSB (2.5 mV). If operating conditions are less than worst case or leakage-induced error is acceptable, larger values

of source resistance is allowable.

—

100

Ω

Table 31. ATD Timing Specifications

Num C

Rating

Symbol

Min

Typ

Max

Unit

D ATD Module Clock Frequency

Fclk

——

25.0

MHz

D ATD Conversion Clock Frequency

Fatdclk

0.5

—

2.0

MHz

D ATD 10-bit Conversion Period*

Clock Cycles

Conv. Time

NCONV10*

TCONV10

14*

—

28*

Cycles*

µsec

D Stop Recovery Time (VDDA = 5.0 V)

TSR

——

100

µsec

Table 32. ATD External Trigger Timing Specifications

Num

Parameter

Symbol

Min

Max

Unit

D ETRIG Minimum Period

TPERIOD

—1 sample +

1 conv. +

1 ATD clock

CYCLE

D ETRIG Minimum Pulse Width

tPW

—

SYS CLK

D ETRIG Level Recovery 1

1 Time prior to end of conversion that the ETRIG pin must be deactivated so that another conversion sequence does

not start.

tLR

—

SYS CLK

D Conversion Start Delay

tDLY

—

SYS CLK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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