TTP259-ASFN datasheet(38/81 Pages) TONTEK

38 / 81 page

Preliminary

TTP259

TonTouch

2015/05/25

Page 38 of 81

Ver: 1.1

.PWM

The PWM period generated from TCP2. When PWMxEN (PWMC<0~2>)

enable, and PWMOUT pin (PA0~PA2,PB0~PB2 must be output mode and

select PWM function pin and normal IO by mask option) change to output

mode, PWMx signal will output to PWMOUT pin. If TCP2 is running, set

PWMxEN=1 will not execute until TCP2OV occur.

The duty of PWMx value is store in PWMxL, PWMxM and PWMxH, user

write PWMxH and PWMxM first, last write PWMxL. When write the PWMxL the

12-bit duty value will be load to PWMxD at the same time. PWM’s duty value

cannot bigger than TCP2 pre-load data. If not, PWMOUT is an unexpected

signal.

User can select PWMOUT pin start with 1 or start with 0 by mask option.

When TCP2 enable, timer start increment, if timer/counter value bigger than

PWM’s duty value, PWMOUT will change state. The PWMOUT back to start

state, When TCP2 is overflow.

User does not use PWM in 20-bit timer/counter mode. If not, PWMOUT is

an unexpected signal.

User does not use TCP2D=000H. If not, PWMOUT is an unexpected signal.

PWMC[00EH]: PWM control register [R/W], default value [-000]

Bit3

Bit2

Bit1

Bit0

Bit Name

PWM2EN

PWM1EN

PWM0EN

Read/Write

R/W

PWM0EN: PWM0 output enable. (0: disable; 1: enable)

PWM1EN: PWM1 output enable. (0: disable; 1: enable)

PWM2EN: PWM2 output enable. (0: disable; 1: enable)

PWM0L[00FH]: PWM0 duty low nibble data register [R/W], default value [xxxx]

Bit3

Bit2

Bit1

Bit0

Bit Name

PWM0D3

PWM0D2

PWM0D1

PWM0D0

Read/Write

R/W

PWM0D3~PWM0D0: PWM0 duty low nibble data.

PWM0M[010H]: PWM0 duty middle nibble data register [R/W], default value [xxxx]

Bit3

Bit2

Bit1

Bit0

Bit Name

PWM0D7

PWM0D6

PWM0D5

PWM0D4

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