TTP259-ASFN datasheet(18/81 Pages) TONTEK

18 / 81 page

Preliminary

TTP259

TonTouch

2015/05/25

Page 18 of 81

Ver: 1.1

Power saving mode condition and release

Modes

Stop mode

Sleep mode

High speed oscillator

Stopped

Stopped as H/L=0

Keep operating as H/L=1

Low speed oscillator

Stopped

Keep operating

CPU clock

Stopped

CPU internal status

Stop and Retain the status

Memory, Flag, Register, IO

Retain the status

Program counter

Hold the next executed address

Peripherals: Time bases,

Timers, Interrupts

Stopped and Retain

Keep operating

Watch Dog Timer

Disable and cleared

Release Condition

Reset, external INT

sources, Input wake-up

Reset, internal and external

INT sources, Input wake-up

S-6: Watch Dog Timer (WDT)

The clock of watch dog timer comes from time base 1st overflow output

(TB1OV).User can use the time up signal to prevent a software malfunction or

abnormal sequence from jumping to an unknown memory location causing a

system fatal failure. Normally, if the watch dog timer time up signal active that

will reset the chip. At the same time, program and hardware can be initialized

and resume system under normal operation. The chip also provides 2 steps

clear watch dog command as the programmer writes INTF with $F data first

that will enable the WDT clear, and then writes CLRWDT register after.

Completely finishes the two write steps will clear the watch dog timer. User

should well arrange the two command steps for avoiding the dead lock loop.

User should keep in minds that always clear the WDT at main

program and never clear the WDT in the interrupt routine.

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