AD7779 datasheet(12/97 Pages) AD

12 / 97 page

AD7779

Data Sheet

Rev. 0 | Page 12 of 97

SAR ADC TIMING CHARACTERISTISTICS

AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− =

2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter

Description1

Min

Typ

Max

Unit

t32

Conversion Time

3.4

μs

t33

Acquisition Time2

500

t34

Delay Time

t35

Throughput Data

256

kSPS

1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.

2 Direct mode enabled. If deglitch mode is enabled, add 1.5/MCLK.

CONVST_SAR

t33

t32

t35

t34

Figure 5. SAR ADC Timing Diagram

GPIO SRC UPDATE TIMING CHARACTERISTISTICS

AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0V, REFx+/REFx− =

2.5 V (internal/external), MCLK = 8192 kHz; all specifications TMIN to TMAX, unless otherwise noted.

Table 6.

Parameter

Description1

Min

Typ

Max

Unit

t36

GPIO2 Setup Time

GPIO2 Hold Time

t37

High Resolution Mode

MCLK

t37

Low Power Mode

2 × MCLK

t38

MCLK Rising Edge to GPIO1 Rising Edge Time

t39

GPIO0 Setup Time

t40

GPIO0 Hold Time

MCLK

1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.

MCLK

GPIO2

GPIO1

GPIO0

t36

t37

t38

t39

t40

Figure 6. GPIOs for SRC Update Timing Diagram

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