AD7779 datasheet(41/97 Pages) AD

41 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 41 of 97

GPIO Pins

If the AD7779 operates in SPI control mode, the mode pins

operate as GPIO pins, as shown in Figure 99. The GPIO pins

can be configured as inputs or outputs in any order.

MAP

GPIO0

GPIO1

GPIO2

Figure 99. GPIO Pin Functionality

Configuration control and readback of the GPIO pins are dealt

with by Bits[2:0] in the GPIO_CONFIG register (0 = input, 1 =

output) and the GPIO_DATA register. Among other uses, the

GPIOs can control an external mux connected to the auxiliary

inputs of the SAR ADC. Use this mux to verify the results on

the -Δ ADCs.

In addition, the GPIO pins can be used to externally trigger a

new decimation rate. Refer to the Sample Rate Converter (SRC)

section for more information about this functionality.

-∆ Reference Configuration

The AD7779 can operate with internal or external references. In

addition, for diagnostic purposes, the analog supply can be used

as a reference, as shown in Table 22.

Table 22. -Δ References

Setting for

ADC_MUX_CONFIG,

Bits[7:6]

Channel 0 to

Channel 3

Channel 4 to

Channel 7

REF1+/REF1−

REF2+/REF2−

Internal reference

AVDD1A/AVSS1A

AVDD1B/AVSS1B

REF1−/REF1+

REF2−/REF2+

Reference buffer operation is described in Table 23. The

selected reference and buffer operation mode affect all

channels.

If the -Δ reference is updated, it is recommended to apply a

pulse on the SYNC_IN pin to remove invalid samples during

the transition of the reference.

Table 23. Reference Buffer Operation Modes

Reference Buffer

Operation Mode

REFx+

REFx−

Enabled

BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 0

BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 0

Precharged

BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 1

BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 1

Disabled

BUFFER_CONFIG_1, Bit 4 = 0

BUFFER_CONFIG_1, Bit 3 = 0

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