ADC16071CIWM datasheet(5/20 Pages) NSC

5 / 20 page

DC Electrical Characteristics

The following specifications apply for VAa e VDa e VMa e 5V unless otherwise specified Boldface limits apply for TA

TJ e TMIN to TMAX all other limits TA e TJ e 25 C

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 6)

(Note 7)

(Limit)

VIH

Logic High Input Voltage

VDa e 525V

VDa

V (max)

V (min)

VIL

Logic Low Input Voltage

VDa e 475V

V (max)

V (min)

VOH

Logic High Output Voltage

Logic High Output Current eb400 mA

V (min)

VDa e 475V

VOL

Logic Low Output Voltage

Logic Low Output Current e 2 mA

V (max)

VDa e 525V

IIN(1)

Logical ‘‘1’’ Input Current

A (max)

IIN(0)

Logical ‘‘0’’ Input Current

A (max)

ITSI

SDO TRI-STATE Leakage Current

VIN e 04V to 24V

A (max)

CIN

Logic Input Capacitance

VIN e 0toVDa

5pF

AC Electrical Characteristics for Clock In (CLK) Serial Clock Out (SCO) and

Frame Sync In (FSI)

The following specifications apply for VAa e VDa e VMa e 5V unless otherwise specified Boldface limits apply for TA

TJ e TMIN to TMAX all other limits TA e TJ e 25 C

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 6)

(Note 7)

(Limit)

fCLK

CLK Frequency Range

MHz (max)

(fCLK e 1tCLK)

MHz (min)

tCLK

CLK Period

1000

ns (max)

(tCLK e 1fCLK)

ns (min)

tCLKL

CLK Low Pulse Width

ns (min)

tCLKH

CLK High Pulse Width

ns (min)

CLK Rise Time

ns (max)

ns (min)

CLK Fall Time

ns (max)

ns (min)

tFSILOW

Minimum Frame Sync Input

2tCLK (min)

Low Time before Frame Sync

Input Asserted High

tFSISU

Frame Sync Input Setup Time

ns (min)

tFSIH

Frame Sync Input Hold Time

ns (min)

tSCOD

Serial Clock Output Delay

ns (max)

Time from Rising Edge

ns (min)

of CLK

tSCO

Serial Clock Output Period

tCLK

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