ADC12L032CIWM datasheet(24/36 Pages) NSC

24 / 36 page

Tables (Continued)

TABLE 6. Conversion/Read Data Only Mode Programming

CONV

Mode

LLL

See

Table 5 for Mode

Read Only (Previous DO Format)

No Conversion

Idle

Power Down

X = Don’t Care

TABLE 7. Status Register

Status

Bit

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

Location

Status

Bit

Cal

8 or 9

12 or 13

16 or 17

Sign

Justification

Test

Mode

Device Status

DO Output Format Status

Function

“High”

indicates

a Power

Sequence

is in

progress

“High”

indicates

a Power

Down

Sequence

is in

progress

“High”

indicates

Auto-Cal

Sequence

is in

progress

“High”

indicates

an8or9

bit format

“High”

indicates

a12or

13 bit

format

“High”

indicates

a16or

17 bit

format

“High”

indicates

that the

sign bit is

included.

When

“Low” the

sign bit is

not

included.

When “High”

the conversion

result will be

output MSB

first. When

“Low” the

result will be

output LSB

first.

When

“High”

the

device is

in test

mode.

When

“Low” the

device is

in user

mode.

Application Hints

1.0 DIGITAL INTERFACE

1.1 Interface Concepts

The example in

Figure 7 shows a typical sequence of events

after the power is applied to the ADC12L030/2/4/8:

The first instruction input to the A/D via DI initiates Auto Cal.

The data output on DO at that time is meaningless and is

completely random. To determine whether the Auto Cal has

been completed, a read status instruction is issued to the

A/D. Again the data output at that time has no significance

since the Auto Cal procedure modifies the data in the output

shift register. To retrieve the status information, an additional

read status instruction is issued to the A/D. At this time the

status data is available on DO. If the Cal signal in the status

word is low Auto Cal has been completed. Therefore, the

next instruction issued can start a conversion. The data out-

put at this time is again status information. To keep noise

from corrupting the A/D conversion, the status can not be

read during a conversion. If CS is strobed and is brought low

during a conversion, that conversion is prematurely ended.

EOC can be used to determine the end of a conversion or

the A/D controller can keep track in software of when it would

be appropriate to communicate to the A/D again. Once it has

been determined that the A/D has completed a conversion

another instruction can be transmitted to the A/D. The data

from this conversion can be accessed when the next instruc-

tion is issued to the A/D.

Note, when CS is low continuously it is important to transmit

the exact number of SCLK cycles, as shown in the timing

diagrams. Not doing so will desynchronize the serial commu-

nication to the A/D (see Section 1.3).

1.2 Changing Configuration

The configuration of the ADC12L030/2/4/8 on power up de-

faults to 12-bit plus sign resolution, 12- or 13-bit MSB First,

10 CCLK acquisition time, user mode, no Auto Cal, no Auto

Zero, and power up mode. Changing the acquisition time

and turning the sign bit on and off requires an 8-bit instruc-

tion to be issued to the ADC. This instruction will not start a

conversion. The instructions that select a multiplexer ad-

dress and format the output data do start a conversion.

Fig-

ure 8 describes an example of changing the configuration of

the ADC12L030/2/4/8.

During I/O sequence 1 the instruction on DI configures the

ADC12L030/2/4/8 to do a conversion with 12-bit +sign reso-

lution. Notice that when the 6 CCLK Acquisition and Data

Out without Sign instructions are issued to the ADC, I/O se-

quences 2 and 3, a new conversion is not started. The data

DS011830-36

FIGURE 7. Typical Power Supply Power Up Sequence

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