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MB9AAA0N bảng dữ liệu(PDF) 86 Page - SPANSION

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Giải thích chi tiết về linh kiện  The MB9AAA0N Series are highly integrated
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D a t a S h e e t
June 30, 2015, MB9AAA0N_DS706-00067-2v0-E
83
CONFIDENTIAL
(10) I
2C Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Parameter
Symbol Conditions
Standard-mode
Fast-mode
Unit Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
CL = 50 pF,
R =
(VP/IOL)*
1
0
100
0
400
kHz
(Repeated) START condition
hold time
SDA   SCL 
tHDSTA
4.0
-
0.6
-
μs
SCL clock L width
tLOW
4.7
-
1.3
-
μs
SCL clock H width
tHIGH
4.0
-
0.6
-
μs
(Repeated) START condition
setup time
SCL   SDA 
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL   SDA  
tHDDAT
0
3.45*
2
0
0.9*
3
μs
Data setup time
SDA    SCL 
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL   SDA 
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
STOP condition and
START condition
tBUF
4.7
-
1.3
-
μs
Noise filter
tSP
-
2 tCYCP*
4
-
2 tCYCP*
4
-
ns
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I
2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies
the requirement of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number which I
2C is connected to, see  Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL



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