MB9AAA0N datasheet(74/109 Pages) SPANSION

74 / 109 page

D a t a S h e e t

June 30, 2015, MB9AAA0N_DS706-00067-2v0-E

CONFIDENTIAL

(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

200

μs

PLL input clock frequency

fPLLI

MHz

PLL multiplication rate

multiplier

PLL macro oscillation clock frequency

fPLLO

MHz

Main PLL clock frequency*

fCLKPLL

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral

Manual.

(4-2) Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input

clock of the Main PLL)

(VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40C to + 85C)

Parameter

Symbol

Value

Unit

Remarks

Min

Typ

Max

PLL oscillation stabilization wait time*

(LOCK UP time)

tLOCK

200

μs

PLL input clock frequency

fPLLI

3.8

4.2

MHz

PLL multiplication rate

multiplier

PLL macro oscillation clock frequency

fPLLO

11.4

16.8

MHz

Main PLL clock frequency*

fCLKPLL

16.8

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral

Manual.

Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency

has been trimmed.

When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account

and prevent the master clock from exceeding the maximum frequency.

High-speed CR clock (CLKHC)

PLL input

clock

Main

PLL

PLL macro

oscillation clock

divider

Main PLL

clock

(CLKPLL)

divider

Main PLL connection

Main clock (CLKMO)

divider

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