3

www.pericom.com

P-0.1

02/27/13

PI6C49021

Low Power High Integration Clock Generator

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Pin List

Pin#

Pin Name

Pin Type

Pin Description

22

OE_PCIE

Input

100MHz HCSL PCIE2 enable pin. Set High to enable.

23

OE_PECL

Input

25MHz LVPECL PECL 25M1 enable pin. Set High to

enable.

25

SE_24M

Output

24MHz LVCMOS output

27

SE_66M0

Output

66.667MHz LVCMOS output

29

SE_66M1

Output

66.667MHz LVCMOS output

33

SE_125M

Output

125MHz LVCMOS output

37

PECL_25M0

Output

25MHz differential output

38

PECL_25M0#

Output

25MHz differential output

40

PECL_25M1

Output

25MHz differential output

41

PECL_25M1#

Output

25MHz differential output

44

PCIE0

Output

100MHz HCSL output

45

PCIE0#

Output

100MHz HCSL output

47

PCIE1

Output

100MHz HCSL output

48

PCIE1#

Output

100MHz HCSL output

Notes: VDD and GND Pins Layout Guide

1. Small value decoupling caps. (0.1uF, 1uF, and 2.2uF) should be placed close each VDD pin or its via

2. Connect all GND pins to package thermal pad which must be connected to the GND plane for better thermal distribution and

signal conducting with reasonable via count (>8)

13-0015