6

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P-0.1

02/27/13

PI6C49021

Low Power High Integration Clock Generator

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Byte 1: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7

OE for SE_125M

RW

1

SE_125M

0 = disabled

1 = enabled

6

OE for SE_50M0

RW

1

SE_50M0

0 = disabled

1 = enabled

5

OE for SE_50M1

RW

1

SE_50M1

0 = disabled

1 = enabled

4

OE for SE_25M0

RW

1

SE_25M0

0 = disabled

1 = enabled

3

OE for SE_25M1

RW

1

SE_25M1

0 = disabled

1 = enabled

2

OE for SE_24M

RW

1

SE_24M

0 = disabled

1 = enabled

1

Spread Spectrum Selection for

100MHz HCSL PCI Express clocks

Bit 1: SS1, Bit 0:SS0

RW

0

All 100MHz HCSL PCI

Express outputs

See Selection Table

2 - Spread Spec-

trum

0

RW

0

Byte 2: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7 to 0

Reserved

R

Undefined

Not Applicable

Byte 0: Bit 6 and Bit 5 Functionality

Bit

Bit 5

Description

0

X

RESET# = "H" will enable all outputs; SMBus can not control each output.

1

0

Disable all outputs and tri-states the outputs. When pin 18 (RESET#) is set low, force device to power-on

reset and set all registers to default values.

1

1

Enable outputs according to the SMBus default values; SMBus can control each output. When pin 18 (RE-

SET#) is set low, force to power-on reset and set all registers to default values.

13-0015