AD9993BBCZ datasheet(35/56 Pages) AD

35 / 56 page

Data Sheet

AD9993

Rev. A | Page 35 of 56

PRBS GENERATOR CONTROL REGISTER

Address: 0x017, Reset: 0x00, Name: PRBS_GEN_CTRL

Table 21. Bit Descriptions for PRBS_GEN_CTRL

Bits

Bit Name

Description

Reset

Access

STROBE_PRBS_RESET

Reset PRBS generator on strobe lane (transfer not needed).

0x0

0 = normal working if PRBS enabled.

1 = reset the PRBS on strobe lane.

STROBE_PRBS_EN

Enable PRBS testing on strobe lane.

0x0

0 = normal mode working with STROBE_DUTY_CYCLE_EN and

STROBE_SAMPLE_RATE.

1 = test mode only.

Note: needs at least one ADC channel working.

DP_PRBS_GEN_RESET

Pseudorandom binary sequence generator reset (transfer not needed,

ADC indexed).

0x0

0 = PRBS generator enabled.

1 = PRBS generator held in reset.

DP_PRBS_GEN_EN

Enable PRBS generating on ADC data lanes (ADC indexed).

0x0

8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 0 REGISTER

Address: 0x020, Reset: 0x01, Name: PRBS0_SEED_MSB

Table 22. Bit Descriptions for PRBS0_SEED_MSB

Bits

Bit Name

Description

Reset

Access

[7:0]

DP_PRBS0_SEED_MSB

8-bit MSB seed of PRBS generator in Lane 0 (ADC indexed).

The 15-bit LSB is always 0x3AFF.

0x1

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