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AD6674 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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AD6674 bảng dữ liệu(HTML) 9 Page - Analog Devices |
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9 / 91 page  Data Sheet AD6674 SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. Parameter Temp AD6674-1000 AD6674-750 AD6674-500 Unit Min Typ Max Min Typ Max Min Typ Max CLOCK Clock Rate (at CLK+/CLK− Pins) Full 0.3 4 0.3 4 0.3 4 GHz Maximum Sample Rate1 Full 1000 750 500 MSPS Minimum Sample Rate2 Full 300 300 300 MSPS Clock Pulse Width High Full 500 666.67 1000 ps Clock Pulse Width Low Full 500 666.67 1000 ps OUTPUT PARAMETERS Unit Interval (UI)3 Full 100 133.33 200 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 25°C 32 32 32 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 25°C 32 32 32 ps PLL Lock Time 25°C 2 2 2 ms Data Rate per Channel (NRZ)4 25°C 3.125 10 12.5 3.125 7.5 12.5 3.125 5 12.5 Gbps LATENCY Pipeline Latency Full 75 75 75 Clock cycles Fast Detect Latency Full 28 28 28 Clock cycles Wake-Up Time (Standby)5 25°C 1 1 1 ms Wake-Up Time (Power-Down)5 25°C 4 4 4 ms APERTURE Aperture Delay (tA) Full 530 530 530 ps Aperture Uncertainty (Jitter, tJ) Full 55 55 55 fs rms Out-of-Range Recovery Time Full 1 1 1 Clock cycles 1 The maximum sample rate is the clock rate after the divider. 2 The minimum sample rate operates at 300 MSPS with L = 2 or L = 1. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 At full baud rate (12.5 Gbps), each ADC outputs data on two differential pair lanes. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode. TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit CLK± to SYSREF± TIMING REQUIREMENTS tSU_SR Device clock to SYSREF± setup time 117 ps tH_SR Device clock to SYSREF± hold time −96 ps SPI TIMING REQUIREMENTS See Figure 4 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK is in a logic high state 10 ns tLOW Minimum period that SCLK is in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 4) 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 4) 10 ns Rev. B | Page 9 of 91 |
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