AT90LS4433-4AI datasheet(52/126 Pages) ATMEL

52 / 126 page

AT90S/LS4433

1042H–AVR–04/03

SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-

ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and

is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set

(one), then by accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write Collision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-

ister with WCOL set (one), and then by accessing the SPI Data Register.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT90S4433 and will always read as zero.

The SPI interface on the AT90S4433 is also used for Program memory and EEPROM

downloading or uploading. See page 93 for Serial Programming and verification.

SPI Data Register – SPDR

The SPI Data Register is a read/write register used for data transfer between the Regis-

ter File and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register Receive buffer to be read.

Bit

7654

321

$0E ($2E)

SPIF

WCOL

–

SPSR

Read/Write

RRRR

RRR

Initial Value

0000

000

Bit

7654

321

$0F ($2F)

MSB

LSB

SPDR

Read/Write

R/W

Initial Value

Undefined

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