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TMS320F28075PZPQ bảng dữ liệu(HTML) 83 Page - Texas Instruments

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TMS320F28075
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SPRS902B – OCTOBER 2014 – REVISED OCTOBER 2015
5.8.1.1
ADC Electrical Data and Timing
Table 5-41. ADC Operating Conditions
over recommended operating conditions (unless otherwise noted)
MIN
TYP
MAX
UNIT
ADCCLK (derived from PERx.SYSCLK)
5
50
MHz
100
ns
Sample window duration (set by ACQPS and PERx.SYSCLK)
1
ADCCLK
VREFHI
2.4
2.5 or 3.0
VDDA
V
VREFLO
VSSA
0
VSSA
V
VREFHI – VREFLO
2.4
VDDA
V
ADC input conversion range
VREFLO
VREFHI
V
NOTE
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input
exceeds this level, the VREF internal to the device may be disturbed, which can impact results
for other ADC or DAC inputs using the same VREF.
Copyright © 2014–2015, Texas Instruments Incorporated
Specifications
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