TMS320F28075PZPQ datasheet(7/182 Pages) TI1

7 / 182 page

TMS320F28075

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SPRS902B – OCTOBER 2014 – REVISED OCTOBER 2015

•

Section 5.8.1.1.2 (ADC Timing Diagrams): Removed "ADC Timings for 12-Bit Mode in Early Interrupt Mode"

figure.

................................................................................................................................ 87

•

Table 5-46 (ADC Timings in 12-Bit Mode (SYSCLK Cycles)): Updated table.

............................................. 88

•

Figure 5-30 (ADC Timings for 12-Bit Mode): Changed figure title from "ADC Timings for 12-Bit Mode in Late

Interrupt Mode" to "ADC Timings for 12-Bit Mode".

............................................................................ 88

•

Section 5.8.1.2 (Temperature Sensor Electrical Data and Timing): Added paragraph.

................................... 89

•

Table 5-47 (Temperature Sensor Electrical Characteristics): Updated description of Start-up time.

................... 89

•

Section 5.8.2 (Comparator Subsystem (CMPSS)): Updated paragraph.

................................................... 90

•

Figure 5-31 (CMPSS Connectivity (176-Pin PTP)): Updated figure.

........................................................ 90

•

Figure 5-32 (CMPSS Connectivity (100-Pin PZP)): Updated figure.

........................................................ 91

•

Section 5.8.2.1 (CMPSS Electrical Data and Timing): Added NOTE about CMPSS inputs.

............................. 92

•

Table 5-48 (Comparator Electrical Characteristics): Updated table.

......................................................... 92

•

Figure 5-33 (CMPSS Comparator Input Referred Offset): Added figure.

................................................... 92

•

Figure 5-34 (CMPSS Comparator Hysteresis): Added figure.

................................................................ 92

•

Table 5-49 (CMPSS DAC Static Electrical Characteristics): Changed table title from "Reference DAC Static

Electrical Characteristics" to "CMPSS DAC Static Electrical Characteristics".

............................................. 93

•

Table 5-49: Changed "DAC" and "reference DAC" to "CMPSS DAC".

..................................................... 93

•

Table 5-49: Added "Per active CMPSS module" footnote.

................................................................... 93

•

Figure 5-35 (CMPSS DAC Static Offset): Added figure.

...................................................................... 93

•

Figure 5-36 (CMPSS DAC Static Gain): Added figure.

........................................................................ 94

•

Figure 5-37 (CMPSS DAC Static Linearity): Added figure.

................................................................... 94

•

Section 5.8.3.1 (Buffered DAC Electrical Data and Timing): Added NOTE about VDAC pin.

........................... 96

•

Table 5-50 (Buffered DAC Electrical Characteristics): Changed table title from "Reference DAC Electrical

Characteristics" to "Buffered DAC Electrical Characteristics".

................................................................ 96

•

Table 5-50: Updated table and footnotes.

....................................................................................... 96

•

Figure 5-39 (Buffered DAC Offset): Added figure.

............................................................................. 97

•

Figure 5-40 (Buffered DAC Gain): Added figure.

............................................................................... 97

•

Figure 5-41 (Buffered DAC Linearity): Added figure.

.......................................................................... 98

•

Section 5.9.1 (Enhanced Capture (eCAP)): Updated section.

............................................................... 99

•

Figure 5-43 (ePWM Submodules and Critical Internal Signal Interconnects): Updated figure and footnotes.

....... 103

•

Figure 5-44 (ePWM Trip Input Connectivity): Changed figure caption from "ePWM" to "ePWM Trip Input

Connectivity".

...................................................................................................................... 104

•

Figure 5-44: Updated figure.

..................................................................................................... 104

•

Table 5-54 (ePWM Switching Characteristics): Changed td(PWM)tza to td(TZ-PWM). ........................................... 106

•

Figure 5-46 (PWM Hi-Z Characteristics): Changed td(TZ-PWM)HZ to td(TZ-PWM)................................................. 106

•

Section 5.9.2.3 (External ADC Start-of-Conversion Electrical Data and Timing): Added section.

..................... 107

•

Section 5.9.3 (Enhanced Quadrature Encoder Pulse (eQEP)): Updated section.

....................................... 108

•

Section 5.9.4 (High-Resolution Pulse Width Modulator (HRPWM)): Updated section.

.................................. 111

•

Section 5.9.5 (Sigma-Delta Filter Module (SDFM)): Updated SDFM features list.

....................................... 112

•

Figure 5-49 (SDFM): Updated figure.

.......................................................................................... 113

•

Table 5-60 (SDFM Timing Requirements): Updated tc(SDC)M0, tc(SDC)M1, tw(SDCH)M1, tc(SDD)M2, and tc(SDC)M3. ............. 114

•

Section 5.10.1 (Controller Area Network (CAN)): Updated NOTE about accuracy of the on-chip zero-pin

oscillator.

........................................................................................................................... 116

•

Section 5.10.2 (Inter-Integrated Circuit (I

2C)): Changed " One 16-word receive FIFO and one 16-word transmit

FIFO" to " One 16-byte receive FIFO and one 16-byte transmit FIFO".

................................................... 117

•

Section 5.10.3 (Multichannel Buffered Serial Port (McBSP)): Updated McBSP featues list.

........................... 120

•

Table 5-63 (McBSP Timing Requirements): Updated footnotes.

........................................................... 122

•

Section 5.10.3.1.2 (McBSP as SPI Master or Slave Timing): Replaced "For all SPI slave modes ..." paragraphs

with "For all SPI slave modes ..." table footnotes.

............................................................................ 125

•

Table 5-65 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)): Added "For all

SPI slave modes ..." footnote.

................................................................................................... 125

•

Table 5-67 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)): Added "For all

SPI slave modes ..." footnote.

................................................................................................... 126

•

Table 5-69 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)): Added "For all

SPI slave modes ..." footnote.

................................................................................................... 127

•

Table 5-71 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)): Added "For all

SPI slave modes ..." footnote.

................................................................................................... 128

•

Section 5.10.5 (Serial Peripheral Interface (SPI)): Changed "High-speed mode for up to 40-MHz full-duplex

communication" to "Changed "High-speed mode for up to 30-MHz full-duplex communication".

...................... 132

•

Table 5-75 (SPI Master Mode External Timings Where (SPIBRR + 1) is Even or SPIBRR = 0 or 2): Parameter 6

Revision History

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