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TPD2S017DBVR bảng dữ liệu(PDF) 8 Page - Texas Instruments

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tên linh kiện TPD2S017DBVR
Giải thích chi tiết về linh kiện  2-Channel Ultra-Low Clamp Voltage ESD Solution
PDF  16 Pages
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Trang chủ  http://www.ti.com
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TPD2S017DBVR bảng dữ liệu(HTML) 8 Page - Texas Instruments

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TPD2S017
SLLS949B – SEPTEMBER 2009 – REVISED DECEMBER 2015
www.ti.com
8.2.2 Detailed Design Procedure
To begin the design process, some parameters must be decided upon; the designer should make sure:
•
Voltage range on the protected lines must not go beyond one forward diode drop above the VCC and must no
go below one forward diode drop below the ground.
•
Operating frequency is supported by the IO capacitance CIO.
•
IEC 61000-4-2 protection requirement is covered by the IEC performance of the TVS diode.
For this application, a high speed USB 2.0 signal that ranges from –10 mV to 440 mV will be applied to each line.
Connect a 5-V power supply to VCC pin; therefore, the signal will not fall outside of the normal operation range
and the TPD2S017 will stay passive and low leakage during normal operation.
Next, consider the data rate of this signal and ensure that the TVS I/O capacitance will not distort this signal by
filtering it. The speed of a USB 2.0 high-speed signal is 480 Mbit/s. With TPD2S017's ultra low IO capacitance,
this device can support 1.5 Gbit/s data rate and thus can pass USB 2.0 high-speed signal with minimal distortion.
Finally, TPD2S017 is rated for the IEC 61000-4-2 (Level 4) so it provides sufficient system-level ESD protection
to the human interface in this application. See Layout Example for instructions on properly laying out TPD2S017.
8.2.3 Application Curves
Figure 7. IEC Clamping Waveforms
Figure 8. IEC Clamping Waveforms
8-kV Contact, 1-GHz Bandwidth
–8-kV Contact, 1-GHz Bandwidth
8
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Product Folder Links: TPD2S017



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