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ST-PLC-AFE bảng dữ liệu(PDF) 28 Page - STMicroelectronics

tên linh kiện ST-PLC-AFE
Giải thích chi tiết về linh kiện  Power-line communication, analog front-end
PDF  58 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST-PLC-AFE bảng dữ liệu(HTML) 28 Page - STMicroelectronics

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SPI interfaces
ST-PLC-AFE
28/58
DocID028727 Rev 1
6
SPI interfaces
The ST-PLC-AFE interface supports SPI mode 0.0 and 1.1. A host SPI frame consists of a
read/write bit, a 3-bit register address, and a 12-data bit register. Data are shifted out on the
falling edge of the SCLK and latched on the rising edge of the SCLK. Refer to Section 6.1:
SPI timing for a valid host and SPI communication protocol.
When nCS = 1, the state machine is reset asynchronously to the R/W state. The nCS does
not need to go high between transfers but, it must be low during the entire transfer. Address
bits identify target registers for writing data. There are three address bits which allow 8 x 12
bit registers, including the DAC register. Received data are stored in the target register on
the 16th edge of the SCLK, if R/W is low.
6.1
SPI timing
Figure 12. SPI mode 0.0



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