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STM32L162VD bảng dữ liệu(PDF) 110 Page - STMicroelectronics

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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32L162VD bảng dữ liệu(HTML) 110 Page - STMicroelectronics

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DocID027268 Rev 3
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 29. WLCSP104, 0.4 mm pitch wafer level chip scale package top view example
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
Table 65. WLCSP104, 0.4 mm pitch recommended PCB design rules
Dimension
Recommended values
Pitch
0.4
Dpad
260 µm max. (circular)
220 µm recommended
Dsm
300 µm min. (for 260 µm diameter pad)
PCB pad design
Non-solder mask defined via underbump allowed.



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